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1 for more information www.linear.com/ltc2862a typical a pplica t ion descrip t ion 60v fault protected 3v to 5.5v rs485/rs422 transceiver with level 4 iec esd rs485 link with large ground loop voltage fea t ures a pplica t ions n protected from overvoltage line faults to 60v n 3v to 5.5v supply voltage n 20mbps or low emi 250kbps data rate n 40kv hbm esd interface pins, 15kv other pins n enhanced receiver and failsafe noise immunity n iec level 4 esd and eft on interface pins n extended common mode range: 25v n guaranteed failsafe receiver operation n high input impedance supports 224 nodes n mp-grade option available (C55c to 125c) n fully balanced differential receiver thresholds for low duty cycle distortion n current limited drivers and thermal shutdown n compliant with tia/eia-485-a n pin compatible with ltc2862 and lt ? 1785 n available in dfn and leaded packages n supervisory control and data acquisition (scada) n industrial control and instrumentation networks n automotive and transportation electronics n building automation, security systems and hvac n medical equipment n lighting and sound system control ltc2862a-1 receiving 10mbps 200mv differential signal with 1mhz 25v common mode sweep part number duplex enables max data rate (bps) lt c28 62 a-1 half yes 20m lt c2862 a-2 half yes 250k the lt c ? 2862a is a low power, 20mbps or 250kbps r s485/ rs422 transceiver operating on 3v to 5.5v supplies with 60v overvoltage fault protection on the interface pins during all modes of operation, including power-down. improvements were made to the ltc2862 for greater ro - bustness and signal integrity : 40kv hbm and level 4 iec esd protection on the interface pins ; increased resistance to electrical overstress; increased receiver noise immunity; additional receiver noise filtering on the ltc2862a-2; and an improved failsafe function optimized for high speed in the ltc2862 a-1 and noise rejection in the ltc2862a-2. low emi slew rate limited data transmission is available in the 250kbps ltc2862a-2 option, while the ltc2862a-1 operates to 20mbps. extended 25v input common mode range and full fail - safe operation improve data communication reliability in electrically noisy environments and in the presence of large ground loop voltages. l , lt, ltc, ltm, linear technology the linear logo and module are registered trademarks of analog devices, inc.. all other trademarks are the property of their respective owners. p ro d uc t s elec t ion gui d e gnd1 gnd2 2862a ta01a ro1 re1 de1 di1 v cc1 ltc2862a ltc2862a v cc2 ro2 re2 de2 di2 d d r r v ground loop 25v peak a,b 50v/div a? b 0.5v/div 100ns/div 2862a ta01b ro 5v/div ro a,b a ? b ltc2862a 2862af
2 for more information www.linear.com/ltc2862a a bsolu t e maxi m u m r a t in g s o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2862acs8-1#pbf ltc2862acs8-1#trpbf 2862a1 8-lead (150mil) plastic so 0c to 70c ltc2862ais8-1#pbf ltc2862ais8-1#trpbf 2862a1 8-lead (150mil) plastic so C40c to 85c ltc2862ahs8-1#pbf ltc2862ahs8-1#trpbf 2862a1 8-lead (150mil) plastic so C40c to 125c ltc2862amps8-1#pbf ltc2862amps8-1#trpbf 2862a1 8-lead (150mm) plastic so C55c to 125c ltc2862acs8-2#pbf ltc2862acs8-2#trpbf 2862a2 8-lead (150mil) plastic so 0c to 70c ltc2862ais8-2#pbf ltc2862ais8-2#trpbf 2862a2 8-lead (150mil) plastic so C40c to 85c ltc2862ahs8-2#pbf ltc2862ahs8-2#trpbf 2862a2 8-lead (150mil) plastic so C40c to 125c ltc2862amps8-2#pbf ltc2862amps8-2#trpbf 2862a2 8-lead (150mm) plastic so C55c to 125c ltc2862acdd-1#pbf ltc2862acdd-1#trpbf lgyk 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2862aidd-1#pbf ltc2862aidd-1#trpbf lgyk 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc2862ahdd-1#pbf ltc2862ahdd-1#trpbf lgyk 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc2862acdd-2#pbf ltc2862acdd-2#trpbf lgym 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2862aidd-2#pbf ltc2862aidd-2#trpbf lgym 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc2862ahdd-2#pbf ltc2862ahdd-2#trpbf lgym 8-lead (3mm 3mm) plastic dfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to : http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ supply voltages v cc ............................................................. C0.3 to 6v logic input voltages ( re , de, di) .................. C 0.3 to 6v interface i/o: a, b ..................................... C 6 0v to + 60v receiver output (ro) ...................... C 0. 3v to (v cc + 0.3v ) operating ambient temperature range (note 4) lt c2862 a c .............................................. 0c to 70 c lt c 2862 ai ........................................... C 40 c to 85 c lt c 2862 a h ....................................... C 40 c to 125 c lt c 2862 a mp ..................................... C 55 c to 125 c storage temperature range .................. C 65 c to 150 c p in c on f i g ura t ion lt c2862 a-1, lt c2862 a-2 lt c2862 a-1, lt c2862 a-2 1 2 3 4 8 7 6 5 top view v cc b a gnd ro re de di s8 package 8-lead (150mil) plastic so t jmax = 150c, ja = 120c/w, jc = 39c/w top view dd package 8-lead (3mm 3mm) plastic dfn exposed pad (pin 9) connect to pcb gnd t jmax = 150c, ja = 43c/w, jc = 5.5c/w 5 6 7 8 9 4 3 2 1ro re de di v cc b a gnd (note 1) http://www.linear.com/product/ltc2862a#orderinfo ltc2862a 2862af
3 for more information www.linear.com/ltc2862a e lec t rical c harac t eris t ics symbol parameter conditions min typ max units supplies v cc primary power supply l 3 5.5 v i ccs supply current in shutdown mode (c-, i-grade) de = 0v, re = v cc l 0 10 a supply current in shutdown mode (h-, mp-grade) de = 0v, re = v cc l 0 40 a i cctr supply current with both driver and receiver enabled (ltc2862a-1) no load, de = v cc , re = 0v l 1.1 1.6 ma i ccr supply current with receiver enabled (ltc2862a-1) no load, de = re = 0v l 1.0 1.4 ma i cctrs supply current with both driver and receiver enabled (ltc2862a-2) no load, de = v cc , re = 0v l 3.5 8 ma i ccrs supply current with receiver enabled (ltc2862a-2) no load, de = re = 0v l 1.3 1.8 ma driver |v od | differential driver output voltage r = (figure 1) l 1.5 3 v cc v r = 27 (figure 1) l 1.5 2 5 v r = 50 (figure 1) l 2 2.3 v cc v |v od | change in magnitude of driver differential output voltage r = 27 or 50 (figure 1) l 0 0.2 v v oc driver common-mode output voltage r = 27 or 50 (figure 1) l 2 3 v |v oc | change in magnitude of driver common-mode output voltage r = 27 or 50 (figure 1) l 0 0.2 v i osd maximum driver short-circuit current C60v (a or b) 60v (figure 2) l 150 250 ma receiver i in receiver input current (a, b) v cc = 0v or 3.3v, v in = 12v (figure 3) l 143 a v cc = 0v or 3.3v, v in = C7v (figure 3) l C100 a r in receiver input resistance 0 v cc 5.5v, v in = C25v or 25v (figure 3) 112 k v cm receiver common mode input voltage (a + b)/2 l C25 25 v v th + positive differential input signal threshold voltage (a C b) C25v v cm 25v l 125 200 mv v th C negative differential input signal threshold voltage (a C b) C25v v cm 25v l C200 C125 mv v th differential input signal hysteresis (v th + C v th C ) v cm = 0v 250 mv v tfs differential input failsafe threshold voltage C25v v cm 25v l C200 C75 C10 mv v tfs differential input failsafe hysteresis (v tfs C v th C ) v cm = 0v 50 mv v oh receiver output high voltage i(ro) = C3ma (sourcing) l v cc C 0.4v v cc C 0.2v v v ol receiver output low voltage i(ro) = 3ma (sinking) l 0.2 0.4 v i ozr receiver three-state (high impedance) output current on ro re = high, v cc = 5v, ro = 0v or v cc l C32 5 a i osr receiver short-circuit current re = low, ro = 0v or v cc l 20 ma c in input capacitance (a and b) (note 5) 50 pf the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v unless otherwise noted. (note 2) ltc2862a 2862af
4 for more information www.linear.com/ltc2862a symbol parameter conditions min typ max units logic v th input threshold voltage (de, di, re ) 3.0 v cc 5.5v l 0.33 ? v cc 0.67 ? v cc v i inl logic input current (de, di, re) 0 v in v cc l 0 5 a esd (note 5) esd protection level of interface pins (a,b), powered or unpowered human body model, a or b to gnd, v cc , b or a, 1f between v cc and gnd 40kv kv iec 61000-4-2 esd level 4, contact, 1f between v cc and gnd 8kv kv esd protection level of all other pins (ro, re, de, di, v cc , gnd) human body model 15kv kv e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v unless otherwise noted. (note 2) symbol parameter conditions min typ max units driver C high speed (ltc2862a-1) f max maximum data rate (note 3) l 20 mbps t plhd , t phld driver input to output r diff = 54, c l = 100pf (figure 4) l 25 50 ns t pd driver input to output difference |t plhd C t phld | r diff = 54, c l = 100pf (figure 4) l 2 5 ns t skewd driver output a to output b r diff = 54, c l = 100pf (figure 4) l 10 ns t rd , t fd driver rise or fall time r diff = 54, c l = 100pf (figure 4) l 4 15 ns t zld , t zhd driver enable time r l = 27, c l = 100pf, re = 0v (figure 5) l 25 50 ns t lzd , t hzd driver disable time r l = 27, c l = 100pf, re = 0v (figure 5) l 45 75 ns t zhsd , t zlsd driver enable from shutdown r l = 27, c l = 100pf, re = high (figure 5) l 5 10 s t shdnd time to shutdown r l = 27, c l = 100pf, re = high (figure 5) l 50 90 ns driver C slew rate limited (ltc2862a-2) f maxs maximum data rate (note 3) l 250 kbps t plhds , t phlds driver input to output r diff = 54, c l = 100pf (figure 4) l 850 1500 ns t pds driver input to output difference |t plhds C t phlds | r diff = 54, c l = 100pf (figure 4) l 10 150 ns t skewds driver output a to output b r diff = 54, c l = 100pf (figure 4) l 500 ns t rds , t fds driver rise or fall time r diff = 54, c l =100pf (figure 4) l 500 800 1200 ns t zlds , t zhds driver enable time r l = 27, c l = 100pf, re = 0v (figure 5) l 400 800 ns t lzds , t hzds driver disable time r l = 27, c l = 100pf, re = 0v (figure 5) l 45 75 ns t zhsds , t zlsds driver enable from shutdown r l = 27, c l = 100pf, re = high (figure 5) l 6 11 s s wi t chin g c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v unless otherwise noted. (note 2) ltc2862a 2862af
5 for more information www.linear.com/ltc2862a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise specified. note 3: maximum data rate is guaranteed by other measured parameters and is not tested directly. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150oc when overtemperature protection is active. continuous operation above the specified maximum operating temperature may result in device degradation or failure. note 5: not tested in production. s wi t chin g c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v unless otherwise noted. (note 2) symbol parameter conditions min typ max units t shdnds time to shutdown r l = 27, c l = 100pf, re = high (figure 5) l 50 90 ns receiver t plhr , t phlr receiver input to output (ltc2862a-1) c l = 15pf , v cm = 0v, |v ab | = 1.5v, t r and t f < 4ns (figure 6) l 50 65 ns t plhrs , t phlrs receiver input to output (ltc2862a-2) c l = 15pf , v cm = 0v, |v ab | = 1.5v, t r and t f < 4ns (figure 6) l 400 700 ns t skewr differential receiver skew |t plhr C t phlr | (ltc2862a-1) c l = 15pf (figure 6) l 1 5 ns t skewrs differential receiver skew |t plhrs C t phlrs | (ltc2862a-2) c l = 15pf (figure 6) l 5 30 ns t pfsn failsafe enter delay (ltc2862a-1) c l = 15pf, v cm = 0v, |v ab | = 1.5v, t r and t f < 4ns (figure 8) l 80 110 ns t pfsns failsafe enter delay (ltc2862a-2) c l = 15pf, v cm = 0v, |v ab | = 1.5v, t r and t f < 4ns (figure 8) l 1.5 2.3 s t pfsx failsafe exit delay (ltc2862a-1) c l = 15pf, v cm = 0v, |v ab | = 1.5v, t r and t f < 4ns (figure 8) l 45 60 ns t pfsxs failsafe exit delay (ltc2862a-2) c l = 15pf, v cm = 0v, |v ab | = 1.5v, t r and t f < 4ns (figure 8) l 0.7 1.3 s t rr , t fr receiver output rise or fall time c l = 15pf (figure 6) l 3 6 ns t zlr , t zhr receiver enable time r l = 500, c l = 15pf , de = high (figure 7) l 18 30 ns t lzr , t hzr receiver disable time r l = 500, c l = 15pf , de = high (figure 7) l 29 40 ns t zhsr , t zlsr receiver enable from shutdown r l = 500, c l = 15pf , de = high (figure 7) l 5 10 s t shdnr time to shutdown r l = 500, c l = 15pf , de = high (figure 7) l 24 40 ns ltc2862a 2862af
6 for more information www.linear.com/ltc2862a typical p er f or m ance c harac t eris t ics driver output short-circuit current vs voltage driver output low/high voltage vs output current driver differential output voltage vs temperature supply current vs data rate driver skew vs temperature driver propagation delay vs temperature t a = 25c, v cc = 3.3v, unless otherwise noted. supply current vs temperature supply current vs v cc output current (ma) 0 0.0 driver output voltage (v) 2.0 1.5 1.0 0.5 2.5 3.0 3.5 10 20 30 40 2862a g07 50 v oh v ol temperature (c) ?50 1.5 v od (v) 1.9 1.7 2.1 2.3 2.5 0 50 100 2862a g08 150 r diff = 100 r diff = 54 temperature (c) driver skew (slew limited) (ns) ?50 ?1.5 driver skew (non slew limited) (ns) 0.0 ?0.5 ?1.0 0.5 1.0 1.5 0 50 100 2862a g04 150 0 60 40 20 100 80 120 slew limited non slew limited r diff = 54 c l = 100pf temperature (c) driver delay (slew limited) (ns) ?50 20 driver delay (non slew limited) (ns) 25 30 35 0 50 100 2862a g05 150 700 800 900 1000 slew limited non slew limited r diff = 54 c l = 100pf v cc (v) 3.0 0 supply current (ma) 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.5 3.5 4.0 4.5 5.0 2862a g01 5.5 4.0 i cctrs i cctr supply current (ma) data rate (slew limited) (kbps) 30 35 0 data rate (non slew limited) (mbps) 8 4 12 16 20 40 45 50 55 2862a g03 60 0 100 50 200 150 250 slew limited non slew limited r diff = 54 c l = 100pf output voltage (v) ?60 ?200 output current (ma) 0 ?50 ?100 ?150 150 100 50 200 ?40 0?20 20 40 2862a g06 60 output low output high temperature (c) ?50 0.1 supply current (a) 10 1 100 10000 0 50 100 2862a g02 150 1000 i cctr i ccs i cctrs receiver output voltage vs output current (source and sink) output current (absolute value) (ma) 0.0 0.0 receiver output voltage (v) 3.0 2.0 1.0 4.0 5.0 6.0 2.0 4.0 6.0 2862a g09 8.0 v cc = 5.5v v cc = 3.3v v cc = 3v to 5.5v ltc2862a 2862af
7 for more information www.linear.com/ltc2862a typical p er f or m ance c harac t eris t ics t a = 25c, v cc = 3.3v, unless otherwise noted. transmitter propagation delay vs temperature (ltc2862a-1) transmitter propagation delay vs temperature (ltc2862a-2) failsafe enter and exit delay vs temperature (ltc2862a-1) failsafe enter and exit delay vs temperature (ltc2862a-2) receiver propagation delay vs temperature (ltc2862a-1) receiver propagation delay vs temperature (ltc2862a-2) ltc2862a 2862af 75 t phlrs t plhrs temperature (c) ?50 ?25 0 25 50 75 100 100 125 300 325 350 375 400 425 450 475 receiver delay (ns) 125 2862a g15 22 24 26 28 30 32 34 t phld transmitter delay (ns) 2862a g10 t phlds t plhds temperature (c) ?50 ?25 0 25 50 t plhd 75 100 125 600 620 640 660 680 700 720 temperature (c) 740 transmitter delay (ns) 2862a g11 t pfsn t pfsx temperature (c) ?50 ?25 0 25 ?50 50 75 100 125 40 50 60 70 80 90 ?25 100 failsafe delay (ns) 2862a g12 t pfsns t pfsxs temperature (c) ?50 ?25 0 25 0 50 75 100 125 0.6 0.8 1.0 1.2 1.4 1.6 25 failsafe delay (s) 2862a g13 t plhr t phlr temperature (c) ?50 ?25 0 25 50 50 75 100 125 40 41 42 43 44 receiver delay (ns) 2862a g14
8 for more information www.linear.com/ltc2862a p in func t ions pin name pin number description ro 1 receiver output. if the receiver output is enabled ( re low) and aCb > 200mv, then ro will be high. if aCb < C200mv, then ro will be low. if the receiver inputs are open, shorted, or terminated without a signal, ro will be high. integrated 250k pull-up to v cc . re 2 receiver enable. a low input enables the receiver. a high input forces the receiver output into a high impedance state. if re is high with de low, the part will enter a low power shutdown state. de 3 driver enable. a high input on de enables the driver. a low input will force the driver outputs into a high impedance state. if de is low with re high, the part will enter a low power shutdown state. di 4 driver input. if the driver outputs are enabled (de high), then a low on di forces the driver noninverting output a low and inverting output b high. a high on di, with the driver outputs enabled, forces the driver noninverting output a high and inverting output b low. gnd 5 ground. exposed pad 9 connect the exposed pad on the dfn packages to gnd. b 7 inverting receiver input and inverting driver output. impedance is ~112k in receive mode or unpowered. a 6 noninverting receiver input and noninverting driver output. impedance is ~112k in receive mode or unpowered. v cc 8 power supply. 3v < v cc < 5.5v. bypass with 1f ceramic capacitor to gnd for best esd performance. ltc2862a logic inputs mode a, b ro de re 0 0 receive r in active 0 1 shutdown r in high-z* 1 0 transceive active active 1 1 transmit active high-z* * 250k pull-up to v cc . func t ion table ltc2862a 2862af
9 for more information www.linear.com/ltc2862a tes t c ircui t s driver di gnd or v cc r a b r 2862a fo1 v od + ? v oc + ? driver di gnd or v cc a b 2862a fo2 i osd + ? receiver b or a a or b v in i in 2862a fo3 + ? v in r in = i in figure?1. driver dc characteristics figure?2. driver output short-circuit current figure?3. receiver input current and input resistance b lock dia g ra m lt c2862 a driver receiver 2862a bd gnd * 40kv esd all other pins 15kv di de re ro 250k v cc v cc a* b* mode control logic ltc2862a 2862af
10 for more information www.linear.com/ltc2862a driver di c l c l a r diff b 2862a fo4 t skewd 1/2 v o t plhd v cc 0v di a, b (a?b) t rd 90% 90% 2862a f04b 10% 10% 0 0 t fd t phld v o figure?4. driver timing measurement driver c l r l r l a de b 2862a fo5 c l di v cc or gnd 1/2 v cc 1/2 v cc t zld , t zlsd t zhd , t zhsd t hzd , t shdn t lzd , t shdn v cc 1/2 v cc 1/2 v cc v ol v oh 1/2 v cc 0v de a or b b or a 2862a f05b 375mv 375mv 375mv 375mv figure?5. driver enable and disable timing measurements tes t c ircui t s ltc2862a 2862af
11 for more information www.linear.com/ltc2862a t es t circui t s receiver c l ro v cm v ab /2 v ab /2 a b 2862a fo6a t plhr t phlr v ab v cc ?v ab a?b ro 0 t rr t fr 90% 90% 2862a f06b 10% 10% 0 1/2 v cc 1/2 v cc t skewr = |t plhr ? t phlr | receiver c l r l ro re a b 2862a fo7a 0v or v cc di = 0v or v cc v cc or 0v 1/2 v cc t zlr , t zlsr t zhr , t zhsr t hzr , t shdnr v cc 1/2 v cc v ol v oh 1/2 v cc 0v re ro ro 2862a f07b t lzr 1/4 v cc 1/4 v cc 3/4 v cc 3/4 v cc 1/2 v cc figure?6. receiver propagation delay measurements figure?7. receiver enable/disable time measurements figure?8. failsafe delay measurements receiver c l ro v cm v ab /2 v ab /2 a b 2862a fo8a t pfsn , t pfsns t pfsx , t pfsxs 0 v cc ?v ab a?b ro 0 2862a f08b ?200mv 1/2 v cc 1/2 v cc ltc2862a 2862af
12 for more information www.linear.com/ltc2862a a pplica t ions i n f or m a t ion 60v fault protection the ltc2862 a is an improved overvoltage fault-tolerant rs485/rs422 transceiver that operates from 3v to 5.5v power supplies. industrial installations may encounter common mode voltages between nodes far greater than the C7v to 12v range specified by the rs485 standards. standard rs485 transceivers can be damaged by voltages above their typical absolute maximum ratings of C8v to 12.5v . the limited overvoltage tolerance of standard r s485 transceivers makes implementation of effective external protection networks difficult without interfering with proper data network performance within the C7v to 12v region of rs485 operation. replacing standard rs485 transceivers with the rugged ltc2862a devices may eliminate field failures due to overvoltage faults without using costly external protection devices. the 60v fault protection of the ltc2862a is achieved by using a high-voltage bicmos integrated circuit technology. the naturally high breakdown voltage of this technology provides protection in powered-off and high-impedance conditions. the driver outputs use a progressive foldback current limit design to protect against overvoltage faults while still allowing high current output drive. the ltc2862 a is protected from 60v faults even with the loss of gnd or v cc (gnd open faults not tested in production). additional precautions must be taken in the case of v cc present and gnd open. the ltc2862a chip will protect itself from damage, but the chip ground current may flow out through the esd diodes on the logic i/o pins and into associated circuitry. the system designer should examine the susceptibility of the associated circuitry to damage if the condition of a gnd open fault with v cc present is anticipated. the high voltage rating of the ltc2862a makes it simple to extend the overvoltage protection to higher levels using external protection components. compared to lower voltage rs485 transceivers, external protection devices with higher breakdown voltages can be used, so as not to interfere with data transmission in the presence of large common mode voltages. the typical applications section shows a protection network against faults up to 360v peak, while still maintaining the extended 25v common mode range on the signal lines. 25v extended common mode range to further increase the reliability of operation and extend functionality in environments with high common mode voltages due to electrical noise or local ground potential differences due to ground loops, the ltc2862a features an extended common mode operating range of C25v to 25v . this extended common mode range allows the ltc2862a to transmit and receive under conditions that would cause data errors and possible device damage in competing products. 40kv esd protection the ltc2862 a features exceptionally robust esd protection. the transceiver interface pins (a,b) feature protection to 40kv hbm with respect to gnd, v cc (with a 1f capacitor to gnd), a or b without latchup or damage, during all modes of operation or while unpowered. all the other pins are protected to 15kv hbm to make this a component capable of reliable operation under severe environmental conditions. level 4 iec esd and eft protection the improved esd protection of the ltc2862a provides a high level of protection in the iec esd and eft (electrical fast transient) tests. the iec esd stress exceeds that of the hbm test in peak current, amplitude, and rise time, while the eft test provides a prolonged repetitive stress. combined with the hbm test, the iec tests help ensure that the ltc2862a is robust under a wide range of real world hazards. the ltc2862a passes the following tests on the a, b pins: ? iec 61000-4- 2 edition 2.0 2008-12 esd level 4 : 8kv contact (a or b to gnd, direct discharge to bus pins with transceiver and protection circuit mounted on a test card with a low impedance ground discharge path from board gnd to esd gun return lead, per figure 4 of the standard) ? iec 61000-4- 4 second edition 2004- 07 eft level 4: 5kv (line to gnd, 5khz repetition rate, 15ms burst duration, 60 second test duration, discharge coupled to bus pins through 100pf capacitor per paragraph 7.3.2 of the standard) ltc2862a 2862af
13 for more information www.linear.com/ltc2862a a pplica t ions i n f or m a t ion enhanced eos protection the improved esd protection of the ltc2862a also pro - vides superior resistance to electrical overstress (eos) damage in the presence of large fault voltages applied from low impedance faults. the ltc2862a employs thyristor type esd protection on the a, b pins. while thyristors have the low on-state impedance and high robustness needed to achieve the very high levels of esd protection of the ltc2862a, they have the disadvantage of snapping back to a low voltage conduction state after they have been triggered by an initial voltage that exceeds ~80v. in the presence of a high voltage, high current fault source, the large resulting currents will blow the bond wires inside the ltc2862a package, resulting in a failed chip. the ltc2862 a mitigates the probability of this type of failure by establishing a very high trigger current in addition to a higher trigger voltage. in order to trigger the esd cell, the fault must not only exceed the ~80v trigger voltage, but must be able to source ~500ma at that voltage to initiate the snapback of the esd cell. this makes the ltc2862a much less susceptible to snapback induced failures created by high voltage noise spikes or voltage transients caused by inductive overshoot when the a,b pins are shorted to a fault voltage source. (the snapback characteristics of the esd protection are not tested during production.) driver the driver provides full rs485/rs422 compatibility. when enabled, if di is high, aCb is positive. when the driver is disabled, both transmitter outputs are high impedance, and the impedance is dominated by the receiver input resistance, r in . driver overvoltage and overcurrent protection the driver outputs are protected from short circuits to any voltage within the absolute maximum range of C60v to 60v. the maximum current in a fault condition is 250ma. the driver includes a progressive foldback current limiting circuit that continuously reduces the driver current limit with increasing output fault voltage. the fault current is less than 15ma for fault voltages over 40v. all devices also feature thermal shutdown protection that disables the driver and receiver in case of excessive power dissipation (see note 4). (thermal shutdown is not tested during production.) full failsafe operation when the absolute value of the differential voltage between the a and b pins is greater than 200mv with the receiver enabled, the state of ro will reflect the polarity of (a Cb). these parts have a failsafe feature that guarantees the receiver output will be in a logic 1 state (the idle state) when the inputs are shorted, left open, or terminated but not driven. the delay allows normal data signals to transition through the threshold region without being interpreted as a failsafe condition. this failsafe feature is guaranteed to work for inputs spanning the entire common mode range of C25v to 25v. most competing devices achieve the failsafe function by a simple negative offset of the input threshold voltage. this causes the receiver to interpret a zero differential voltage as a logic 1 state. the disadvantage of this approach is the input offset can introduce duty cycle asymmetry at the receiver output that becomes increasingly worse with low input signal levels and slow input edge rates. other competing devices use internal biasing resistors to create a positive bias at the receiver inputs in the absence of an external signal. this type of failsafe biasing is ineffective if the network lines are shorted, or if the network is terminated but not driven by an active transmitter. figure?9. duty cycle of balanced receiver with 200mv 10mbps input signal a, b 200mv/div a?b 200mv/div 40ns/div 286a f08 ro 1.6v/div ltc2862a 2862af
14 for more information www.linear.com/ltc2862a the ltc2862 a uses fully symmetric positive and negative receiver thresholds v th C and v th + (typically 125mv) to maintain good duty cycle symmetry at low signal levels. the failsafe operation is performed with a window comparator to determine when the differential input voltage falls above the v tfs failsafe threshold (typically C75mv ) but below the v th + threshold. if this condition persists for more than about 40ns for the ltc2862a-1 or 1.2s for the ltc2862 a-2 the failsafe condition is asserted and the ro pin is forced to the logic 1 state. this circuit provides full failsafe operation and a large dynamic signal hysteresis of ~250mv between v th C and v th + with no negative impact to receiver duty cycle symmetry, as shown in figure?9. the input signal in figure? 9 was obtained by driving a 10mbps rs485 signal through 1000 feet of cable, thereby attenuating it to a 200mv signal with slow rise and fall times. good duty cycle symmetry is observed at ro despite the degraded input signal. the failsafe circuit has been enhanced with noise filtering to exit the failsafe state. in the absence of noise filtering, a noise transient that momentarily forces the a-b differential voltage below the v th C receiver threshold will cause the ro output to go low, which may be interpreted as a false start character by the microcontroller. the ltc2862a receiver reduces these false signals by low pass filtering the signal to exit the failsafe state. the noise filtering in the failsafe circuit of the ltc2862a-2 is much greater than in the ltc2862 a-1, commensurate with its lower data rate. for example, the ltc2862a-1 exits the failsafe state when a C1v differential pulse of about 3ns duration is applied, while the ltc2862a-2 requires a C1v pulse of about 400ns duration to exit the failsafe state. (the minimum pulse widths to enter or exit the failsafe state are not tested in production, but the underlying filtering is reflected in the t fsn , t fsx , t fsns , and t fsxs measurements). enhanced receiver noise immunity an additional benefit of the fully symmetric receiver thresholds is enhanced receiver noise immunity. the differential input signal must go above the positive threshold to register as a logic 1 and go below the negative threshold to register as a logic 0. this provides a hysteresis of 250mv (typical) at the receiver inputs for any valid data signal. (an invalid data condition such as a dc sweep of the receiver inputs will produce a different observed hysteresis due to the activation of the failsafe circuit.) competing devices that employ a negative offset of the input threshold voltage generally have a much smaller hysteresis and subsequently have lower receiver noise immunity. the ltc2862 a-2 provides additional noise immunity by adding low-pass filtering to the differential signal in its receiver. commensurate with its maximum data rate of 250kbps , the ltc2862a-2 receiver attenuates high frequency signals above approximately 660khz. this low- pass filter removes high frequency noise transients that might otherwise be interpreted as data. (high frequency noise filtering is not tested in production, but the underlying filtering is reflected in the t plhr , t phlr , t plhrs , and t phlrs measurements). rs485 network biasing rs485 networks are usually biased with a resistive divider to generate a differential voltage of 200mv on the data lines, which establishes a logic 1 state (the idle state) when all the transmitters on the network are disabled. the values of the biasing resistors are not fixed, but depend on the number and type of transceivers on the line and the number and value of terminating resistors. therefore, the values of the biasing resistors must be customized to each specific network installation, and may change if nodes are added to or removed from the network. the internal failsafe feature of the ltc2862 a eliminates the need for external network biasing resistors provided they are used in a network of transceivers with similar internal failsafe features. the ltc2862a transceivers will operate correctly on biased, unbiased, or under-biased networks. hi-z state the receiver output is internally driven high (to v cc ) or low (to gnd) with no external pull-up needed. when the receiver is disabled the ro pin becomes hi-z with a 250k pull-up resistor to v cc . a pplica t ions i n f or m a t ion ltc2862a 2862af
15 for more information www.linear.com/ltc2862a high receiver input resistance the bus receiver input load from a or b to gnd is less than one-seventh unit load, permitting a total of 224 receivers per system without exceeding the rs485 receiver loading specification. the input load of the receiver is unaffected by enabling/disabling the receiver or by powering/unpowering the part. supply current the unloaded static supply currents in these devices are low typically 1.1ma for non slew limited devices and 3.5ma for slew limited devices. in applications with resistively terminated cables, the supply current is dominated by the driver load. for example, when using two 120? terminators with a differential driver output voltage of 2v , the dc load current is 33ma, which is sourced by the positive voltage supply. power supply current increases with toggling data due to capacitive loading and this term can increase significantly at high data rates. a plot of the supply current vs data rate is shown in the typical performance characteristics of this data sheet. during fault conditions with a positive voltage larger than the supply voltage applied to the transmitter pins, or during transmitter operation with a high positive common mode voltage, positive current of up to 80ma may flow from the transmitter pins back to v cc . if the system power supply or loading cannot sink this excess current, a 5.6v 1w 1n4734 zener diode may be placed between v cc and gnd to prevent an overvoltage condition on v cc . the ltc2862 a contains a supply undervoltage lockout circuit that enables the transmitter and receiver outputs when v cc exceeds ~2.7v and disables the transmitter and receiver outputs when v cc falls below ~2.5v. when the ltc2862a is unpowered, the logic inputs (de, di, re) are high impedance for voltages > 0v. each input has a diode clamp to gnd that will conduct if a negative voltage sufficient to forward bias the diode ( ~ C 0.6v at 25 c ) is applied to the pad. the ro output contains a cmos driver with parasitic diodes to gnd and v cc . the diode to gnd will conduct if forward biased by a negative voltage below gnd, while the diode to v cc will conduct if forward biased by a positive voltage above v cc . if v cc is low, this a pplica t ions i n f or m a t ion will result in the ro line being clamped to approximately 0.6v above v cc . the impedance of the logic inputs and the ro output are not tested with the ltc2862a unpowered. shutdown mode delay the ltc2862 a features a low power shutdown mode that is entered when both the driver and the receiver are simultaneously disabled (pin de low and re high). a shutdown mode delay of approximately 250ns (not tested in production) is imposed after this state is received before the chip enters shutdown. if either de goes high or re goes low during this delay, the delay timer is reset and the chip does not enter shutdown. this reduces the chance of accidentally entering shutdown if de and re are driven in parallel by a slowly changing signal or if de and re are driven by two independent signals with a timing skew between them. this shutdown mode delay does not affect the outputs of the transmitter and receiver, which start to switch to the high impedance state upon the reception of their respec- tive disable signals as defined by the parameters t shdnd and t shdnr . the shutdown mode delay affects only the time when all the internal circuits that draw dc power from v cc are turned off. high speed considerations a ground plane layout with a 0.1f bypass capacitor placed less than 7mm away from the v cc pin is recommended. the pc board traces connected to signals a/b should be symmetrical and as short as possible to maintain good differential signal integrity. to minimize capacitive effects, the differential signals should be separated by more than the width of a trace and should not be routed on top of each other if they are on different signal planes. care should be taken to route outputs away from any sensitive inputs to reduce feedback effects that might cause noise, jitter, or even oscillations. the logic inputs have a typical hysteresis of 100mv to provide noise immunity. fast edges on the outputs can cause glitches in the ground and power supplies which are exacerbated by capacitive loading. if a logic input is held near its threshold (typically v cc / 2), a noise glitch from a ltc2862a 2862af
16 for more information www.linear.com/ltc2862a driver transition may exceed the hysteresis levels on the logic and data input pins, causing an unintended state change. this can be avoided by maintaining normal logic levels on the pins and by slewing inputs faster than 1v/s. good supply decoupling and proper driver termination also reduce glitches caused by driver transitions. r s485 cable length vs data rate m any factors contribute to the maximum cable length that can be used for r s485 or r s422 communication, including driver transition times, receiver threshold, duty cycle distortion, cable properties and data rate. a typical curve of cable length versus maximum data rate is shown in figure?10. various regions of this curve reflect different performance limiting factors in data transmission. at frequencies below 100kbps , the maximum cable length is determined by dc resistance in the cable. in this example, a cable longer than 4000ft will attenuate the signal at the far end to less than what can be reliably detected by the receiver. for data rates above 100kbps the capacitive and inductive properties of the cable begin to dominate this relationship. the attenuation of the cable is frequency and length dependent, resulting in increased rise and fall times at the far end of the cable. at high data rates or long cable lengths, these transition times become a significant part of the signal bit time. jitter and intersymbol interference aggravate this so that the time window for capturing valid data at the receiver becomes impossibly small. the boundary at 20mbps in figure? 10 represents the guaranteed maximum operating rate of the lt c2862 a-1. the dashed vertical line at 10mbps represents the specified maximum data rate in the r s485 standard. this boundary is not a limit, but reflects the maximum data rate that the specification was written for. it should be emphasized that the plot in figure?10 shows a typical relation between maximum data rate and cable length. results with the lt c2862 a will vary, depending on cable properties such as conductor gauge, characteristic impedance, insulation material, and solid versus stranded conductors. low emi 250kbps data rate the ltc2862 a-2 features slew rate limited transmitters for low electromagnetic interference (emi) in sensitive applications. the slew rate limit circuit maintains consistent control of transmitter slew rates across voltage and temperature to ensure low emi under all operating conditions. figure? 11 demonstrates the reduction in high frequency content achieved by the 250kbps mode compared to the 20mbps mode. the 250kbps mode has the added advantage of reducing signal reflections in an unterminated network, and there- by increasing the length of a network that can be used without termination. using the rule of thumb that the rise time of the transmitter should be greater than four times the one-way delay of the signal, networks of up to 140 feet can be driven without termination. a pplica t ions i n f or m a t ion figure?10. cable length vs data rate (rs485/rs422 standard shown in vertical dashed line) figure?11. high frequency emi reduction of slew limited 250kbps mode compared to non slew limited 20mbps mode data rate (bps) 10k 10 cable length (ft) 100 1k 10k 100k 1m 10m 2862a f10 100m low emi mode ltc2862a-2 rs485 standard spec frequency (mhz) 0 ?120 a?b (non slew limited) (db) ?40 ?60 ?80 ?100 ?20 0 20 ?60 a?b (slew limited) (db) 20 0 ?20 ?40 40 60 80 2 4 6 8 10 2862a f11 12 non slew limited slew limited ltc2862a 2862af
17 for more information www.linear.com/ltc2862a a pplica t ions i n f or m a t ion profibus compatible interface profibus is an rs485 -based field bus. in addition to the specifications of tia/eia-485-a, the profibus specification contains additional requirements for cables, interconnects, line termination, and signal levels. the following discussion applies to the profibus type a cables with associated connectors and termination. the type a cable is a twisted pair shielded cable with a characteristic impedance of 135? to 165? and a loop resistance of < 110/km. the ltc2862 a rs485 transceiver may be used in profibus compatible equipment if the following considerations are implemented. (please refer to the schematic of the profibus compatible interface in the typical applications section.) 1. the polarity of the profibus signal is opposite to the polarity convention used in this data sheet. the pro - fibus b wire is driven by a non-inverted signal, while the a wire is driven by an inverted signal. therefore, it is necessar y to swap the output connections from the transceiver . pin a is connected to the profibus b wire, and pin b is connected to the profibus a wire. 2. each end of the profibus line is terminated with a 220 resistor between b and a, a 390 pull-up resistor between b and v cc , and a 390 pull-down resistor between a and gnd. this provides suitable termination for the 150 twisted pair transmission cable. 3. the peak to peak differential voltage v od received at the end of a 100m cable with the cable and termina - tions described above must be greater than 4v and less than 7v . the ltc2862a produces signal levels in excess of 7v when driving this network directly. 8.2? resistors may be inserted between the a and b pins of the transceiver and the b and a pins of the profibus cable to attenuate the transmitted signal to meet the profibus upper limit of 7v while still providing enough drive strength to meet the lower limit of 4v. 4. the ltc2862 a transceiver should be powered by a 5% tolerance 5v supply (4.75v to 5.25v) to ensure that the profibus v od tolerances are met. auxiliary protection for 5kv surge, 5kv eft, and 30kv iec esd an interface transceiver used in an industrial setting may be exposed to extremely high levels of electrical overstress due to phenomena such as lightning surge, electrical fast transient (eft) from switching high current inductive loads, and electrostatic discharge (esd) from the discharge of electrically charged personnel or equipment. test methods to evaluate immunity of electronic equipment to these phenomena are defined in the iec standards 61000-4-2, 61000-4-4, and 61000-4-5, which address esd, eft, and surge, respectively. the transients produced by the eft and particularly the surge tests contain much more energy than the esd transients. the ltc2862 a is designed for high robustness against esd, but the on-chip protection is not able to absorb the energy associated with the 61000-4-5 surge transients. therefore, a properly designed external protection network is necessary to achieve a high level of surge protection, and can also extend the esd and eft performance of the ltc2862a to extremely high levels. in addition to providing surge, eft and esd protection, an external network should preserve or extend the ability of the ltc2862a to withstand overvoltage faults, operate over a wide common mode, and communicate at high frequencies. in order to meet the first two requirements, protection components with suitably high conduction voltages must be chosen. a means to limit current must be provided to prevent damage in case a secondary protection device or the esd cell on the ltc2862 a fires and conducts. the capacitance of these components must be kept low in order to permit high frequency communication over a network with multiple nodes. meeting the requirements for conducting very high energy electrical transients while maintaining high hold-off voltages and low capacitance is a considerable challenge. ltc2862a 2862af
18 for more information www.linear.com/ltc2862a a protection network shown in the typical applications section (network for iec level 4 protection against 5kv surge, 5kv eft and 30kv iec esd plus 360v overvoltage protection) meets this challenge. the network provides the following protection: ? iec 61000-4- 2 esd level 4 : 30kv contact, 30kv air (line to gnd, direct discharge to bus pins with transceiver and protection circuit mounted on a ground referenced test card per figure 4 of the standard) ? iec 61000-4- 4 eft level 4 : 5kv (line to gnd, 5khz repetition rate, 15ms burst duration, 60 second test duration, discharge coupled to bus pins through 100pf capacitor per paragraph 7.3.2 of the standard) ? iec 61000-4- 5 surge level 4 : 5kv (line to gnd, line to line, 8/ 20s waveform, each line coupled to generator through 80 resistor per figure 14 of the standard) this protection circuit adds only ~8pf of capacitance per line (line to gnd), thereby providing an extremely high level of protection without significant impact to the performance of the ltc2862a transceivers at high data rates. a pplica t ions i n f or m a t ion the gas discharge tubes (gdts) provide the primary protection against electrical surges. these devices provide a very low impedance and high current carrying capability when they fire, safely discharging the surge current to gnd. the transient blocking units (tbus) are solid state devices that switch from a low impedance pass through state to a high impedance current limiting state when a specified current level is reached. these devices limit the current and power that can pass through to the secondary protection. the secondary protection consists of a bidirectional thyristor, which triggers above 35v to protect the bus pins of the ltc2862 a transceiver. the high trigger voltage of the secondary protection maintains the full 25v common mode range of the receivers. the final component of the network is the metal oxide varistors (movs) which are used to clamp the voltage across the tbus to protect them against fast esd and eft transients which exceed the turn-on time of the gdt. the high performance of this network is attributable to the low capacitance of the gdt and thyristor primary and secondary protection devices. the high capacitance mov floats on the line and is shunted by the tbu, so it contributes no appreciable capacitive load on the signal. ltc2862a 2862af
19 for more information www.linear.com/ltc2862a failsafe o application (idle state = logic o) 60v 20mbps level shifter/isolator di gnd v cc v cc1 ltc2862a-1 v cc2 r2 60v r1 a b r1 = 200k 1%. place r1 resistors near a and b pins of receiver. r2 = 10k c = 47pf, 5%, 50 wvdc. may be omitted for data rates < 100kbps. data in 1 data out 1 v cc ro ltc2862a-1 gnd c a b 2862a ta03 r1 c d r profibus compatible line interface typical a pplica t ions ro re de di 8.2 2862a ta02 a* r b* * the polarity of a and b in this data sheet is opposite the polarity defined by profibus. v cc (4.75v to 5.25v) gnd ltc2862a 8.2 390 4v p-p v od 7v p-p up to 1500kbps 220 390 b wire a wire b wire a wire v cc 390 220 390 v cc 100m 5.5/wire v od d 2862a ta04 ro de di ro de di b r i1 5v a ?a? ?b? gnd v cc ltc2862a d i2 ltc2862a 2862af
20 for more information www.linear.com/ltc2862a dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) p acka g e descrip t ion please refer to http://www.linear.com/product/ltc2862a#packaging for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc ltc2862a 2862af
21 for more information www.linear.com/ltc2862a information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p acka g e descrip t ion .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0? 8 typ .008 ? .010 (0.203 ? 0.254) so8 rev g 0212 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) 4. pin 1 can be bevel edge or a dimple s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610 rev g) s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610 rev g) please refer to http://www.linear.com/product/ltc2862a#packaging for the most recent package drawings. ltc2862a 2862af
22 for more information www.linear.com/ltc2862a ? linear technology corporation 2017 lt 0617 ? printed in usa www.linear.com/ltc2862a r ela t e d p ar t s typical a pplica t ion part number description comments lt1785, lt1791 60v fault protected rs485/rs422 transceivers 60v tolerant, 15kv esd, 250kbps ltc2863/ltc2864/ ltc2865 60v fault protected 3v to 5.5v rs485/rs422 transceivers 60v tolerant, 15kv esd, 20mbps or 250kbps ltc2877 60v rugged profibus rs485 transceivers profibus iec 61158-2 compliant, 52kv esd lt m ? 2885 6500v rms isolated rs485/rs422 module ? transceiver + power 6500v rms for 1 minute, isolated power: 5v at 150ma ltc2850/ltc2851/ ltc2852 3.3v 20mbps 15kv rs485 transceivers up to 256 transceivers per bus ltc2854, ltc2855 3.3v 20mbps rs485 transceivers with integrated switchable termination 25kv esd (ltc2854), 15kv esd (ltc2855) ltc2856-1 family 5v 20mbps and slew rate limited rs485 transceivers 15kv esd ltc2859, ltc2861 5v 20mbps rs485 transceivers with integrated switchable termination 15kv esd ltc1535 isolated rs485 transceiver 2500v rms isolation, requires external transceiver LTM2881 complete 3.3v isolated rs485/rs422 module transceiver + power 2500v rms isolation with integrated isolated dc/dc converter, 1w power, low emi, 15kv esd, 30kv/s common mode transient immunity network for iec level 4 protection against 5kv surge, 5kv eft and 30kv iec esd plus 360v overvoltage protection 2862a ta05 v cc de scr gdt scr a b di ltc2862a-1 gdt: bourns 2031-42t-sm; 420v gas discharge tube tbu: bourns tbu-ca085-300-wh; 850v transient blocking unit mov: bourns mov-7d391k; 390v 25j metal oxide varistor scr: bourns tisp4p035l1nr-s; 35v bidirectional thyristor ro d r gnd re mov mov tbu tbu gdt gnd rs485 a (external) rs485 b (external) ltc2862a 2862af

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